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发信人: jjk (Linux Device Driver), 信区: Linux
标 题: Flat memory models + BIOS addresses(转寄)
发信站: 荔园晨风BBS站 (Wed May 15 13:19:57 2002), 转信
【 以下文字转载自 jjk 的信箱 】
【 原文由 jjk.bbs@apue.dhs.org 所发表 】
发信人: ysqcn (岁月无声), 信区: UKP
标 题: Flat memory models + BIOS addresses
发信站: UNIX编程 (2001年11月24日14:35:34 星期六), 站内信件
Message 1 in thread
寄件者：William Lane (wlane@engr.csulb.edu)
主旨：Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1997/12/16
I had a brief question about the
80x86 architecture and the fact that ROM-
BIOS, the video BIOS, NIC BIOS etc. are
all mapped into main memory. Do the Pentium
class systems (I've only worked w/486's)
still maintain this same bizarre addressing
scheme? If so how can you have a flat memory
model if you have to jump over the post
640k but under 1024k BIOS mapped region?
Is it the job of the compiler or the OS
to make sure that a program doesn't try
to use the HMA (or whatever it's called)
for code/data? Is this design flaw (i.e.
splitting BIOS data in two different areas
of memory) present in other CPU designs?
Is this feature of the x86 architecture
due to Intel or IBM? Will this feature be
eliminated w/the advent of the IA64
architecture?
sorry if it's not really
a brief question...
-Bill
寄件者：ccrayne@pacific.net (ccrayne@pacific.net)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View: Complete Thread (12 articles) | Original Format
日期：1997/12/16
[This followup was posted to comp.lang.asm.x86 and a copy was sent to
the cited author.]
In <34999080.3717961@news.magicnet.net>, on 12/16/97
at 02:30 PM, wlane@engr.csulb.edu (William Lane) said:
: I had a brief question about the
:80x86 architecture and the fact that ROM-
:BIOS, the video BIOS, NIC BIOS etc. are
:all mapped into main memory.
There are a number of reasons why this is not a problem. I have touched
on some of them in response to your specific question, but feel free to
carry on the discussion if you want more information.
: Do the Pentium
:class systems (I've only worked w/486's)
:still maintain this same bizarre addressing
:scheme?
This is not a function of the CPU, but rather a carry-over from the
original IBM PC design, which is necessary for software compatability in
real mode.
:If so how can you have a flat memory
:model if you have to jump over the post
:640k but under 1024k BIOS mapped region?
Flat memory model means that your program can address everything it is
allowed to touch without having to worry about segment registers. What
the OS, the BIOS, or the hardware is actually doing is (for the most
part) none of your program's business.
:Is it the job of the compiler or the OS
:to make sure that a program doesn't try
:to use the HMA (or whatever it's called)
:for code/data?
It is the job of a protected mode OS to present your program with a flat
memory model, even though the actual hardware is a segment:offset model.
The compiler has nothing to do with this. In real mode operating
systems, nothing stops you from using high memory for you any purpose
you want.
: Is this design flaw (i.e.
:splitting BIOS data in two different areas
:of memory) present in other CPU designs?
The CPU design has very little to do with the issue, other than the size
of the virtual address space which it can access. The various BIOS
addresses must be mapped into memory at some address in order to run,
and certain hardware components (such as display buffers) are much
faster if they are mapped into memory, instead of I/O ports.
In general, system designers assign program memory from the bottom up,
and BIOS and device memory from the top down, leaving a hole in the
middle for expansion. This causes no problems until the CPU
addressability is increased. By then, it's too late to move the hardware
addresses, because it makes the new system incompatable with existing
software.
:Is this feature of the x86 architecture
:due to Intel or IBM?
As it has nothing to do with x86 architecture per se, Intel had nothing
to do with it. IBM's design was quite reasonable for the time, and it
still creates no problems when running under a protected mode operating
system.
: Will this feature be
:eliminated w/the advent of the IA64
:architecture?
Highly unlikely.
Best,
-- Chuck Crayne
寄件者：George C. Lindauer (gclind01@spd.louisville.edu)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View: Complete Thread (12 articles) | Original Format
日期：1997/12/17
William Lane (wlane@engr.csulb.edu) wrote:
> I had a brief question about the
> 80x86 architecture and the fact that ROM-
> BIOS, the video BIOS, NIC BIOS etc. are
> all mapped into main memory. Do the Pentium
> class systems (I've only worked w/486's)
> still maintain this same bizarre addressing
> scheme? If so how can you have a flat memory
> model if you have to jump over the post
> 640k but under 1024k BIOS mapped region?
well 'flat' here refers to the fact of having
all the segments mapped with a base address of
zero, not to the chunkability of memory. In cases
where that is a problem it is easy enough to enable
the paging mechanism to get around it.
> Is it the job of the compiler or the OS
> to make sure that a program doesn't try
> to use the HMA (or whatever it's called)
> for code/data? Is this design flaw (i.e.
> splitting BIOS data in two different areas
> of memory) present in other CPU designs?
the OS. This whole thing came about for
historical reasons... back when the PC was designed
the processor could not access more than 1MB of memory
(the HMA wrapped around to low memory, too) and
there wasn't a chunk issue. With the advent of new
processors they had to continue with the original
design because they didn't want to upset old
software. However, it is fairly easy to deal with
e.g. viat hte paging mechanism... but that of
course raises other issues since the DMA subsystem
is also a limiting factor.
Some other CPUs have similar problems, again for
historical reasons. When a CPU is new it is fairly
common to reserve memory at either the bottom of
the address range or the top or sometimes both
when the architecture demands it... and leave
the ram in between contiguous. This IS what waz
done originally, but, in our effort to make
things better while allowing legacy software
to run some compromises had to be made.
> Is this feature of the x86 architecture
> due to Intel or IBM? Will this feature be
> eliminated w/the advent of the IA64
> architecture?
A combination. Intel's original 8086 called for
reserving at least a few bytes at the top and
then having the bottom reserved for the vector
table. IBM then acme up with the exact
architecture. With the advent of the 286 and more
memory, they couldn't move the BIOS area to the
top of the new memory because it would have broken
existing programs. Inmtel and the PC vendors
of the time then came up with support for
the current scheme that has chunked memory.
This is a PC issue... if you design your own
computer you can do pretty much what
you want with it. In particular the processor
is STILL set up to boot out of the very top of
memory, and while this isn't entirely compatible with
real mode you COULD do a hardware workaround
that moved you into a 32-bit segment and left
all the ram contiguous with a base of zero.
But I wouldn't design around an x86, it is
a fairly lousy processor and would have
died as a natural result of evolution
if bill gates hadn't grabbed it as part of
his plans and nurtured it.
david
> sorry if it's not really
> a brief question...
> -Bill
寄件者：Jer (milosek@prodigy.net)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1997/12/18
Gentlemen,
Your discussion has prompted me to ask you this question. How does
Shadow Ram work? I know using shadow ram is intended to use system
memory in place of the adapters memory because its faster, but if
shadow ram is not enabled, how does the system "know" to access the
storage on the adapter card? If I access a storage location that can
be shadow ram, how do I know if the data comes from system memory or
the adapters memory? What is it in the machine that determines where
this data will come from?
Pardon my asking in this thread, but its the closest I've come
across that approaches my questions.
Thanks for your time, Jer
not enabled
件者：John S. Fine (johnfine@erols.com)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1997/12/18
Jer wrote:
> Your discussion has prompted me to ask you this question. How does
> Shadow Ram work? I know using shadow ram is intended to use system
> memory in place of the adapters memory because its faster, but if
> shadow ram is not enabled, how does the system "know" to access the
There are registers in the "chipset" that control where acceses in the
upper 384Kb of the first Mb go. For Intel PCI chipsets and the AMD 640,
these registers are well documented in PDF files on their web pages.
For other chipsets the documentation is not easy to get.
Generally the BIOS sets up which ranges are shadowed during bootup and
nothing changes that afterward.
> storage on the adapter card? If I access a storage location that can
> be shadow ram, how do I know if the data comes from system memory or
> the adapters memory? What is it in the machine that determines where
If you have chipset documentation you just read the registers and see
what was set up (My PCI.EXE program will report that information for
some Intel chips and the SiS 5571. I have that information for the AMD
640 and some Via and additional Intel chipsets, but haven't added
support to the program yet.) If you don't have chipset documentation,
you might try timing acesses (be carefull of cache). Shadow ram should
always be measurably faster than PCI bus rom and faster still versus ISA
bus rom.
寄件者：William Lane (wlane@engr.csulb.edu)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1997/12/22
I now have a variant on my original
question, assuming we now have a "flat" memory
model, how are the interrupt vectors resolved?
I've been reading that the interrupt vectors
are in segment:offset notation, which would
be meaningless if using absolute, 32-bit
addressing schemes right? If all addressing
in 32-bit OS's is 32-bit what use are the
various segment registers? Can segment registers
be used as G.P. registers on the 80386 and
above processors (when in protected mode)?
I can really see why my basic 80x86
assembly text states something to the effect
that the protected mode instructions of the 80386
and above processors are "beyond the scope of
this book."
This whole newsgroup has made me really
question the method by which assembly is taught
at CSULB, but then again maybe I don't know
enuff' to really comment at all...
-Bill Lane
Computer "Engineeing" student
寄件者：ccrayne@pacific.net (ccrayne@pacific.net)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View: Complete Thread (12 articles) | Original Format
日期：1997/12/22
Bill - In order to enhance the logical flow of my answers, I have taken
the liberty of rearranging your questions. In addition, I am sending you
an email copy of my post.
In <34a68000.2617127@news.magicnet.net>, on 12/22/97
at 02:57 PM, wlane@engr.csulb.edu (William Lane) said:
: This whole newsgroup has made me really
:question the method by which assembly is taught
:at CSULB, but then again maybe I don't know
:enuff' to really comment at all...
Regardless of the current quality of the CSULB cirriculum, I have no
doubt that it would be improved if I were in charge of the department.
:) However, this is not so much an assembly language issue as it is an
operating system design issue.
:If all addressing
:in 32-bit OS's is 32-bit what use are the
:various segment registers?
None whatsoever! At least not at the user level. The innards of the OS
are a different matter entirely.
: Can segment registers
:be used as G.P. registers on the 80386 and
:above processors (when in protected mode)?
Not a chance! The Intel 80x86 family has always been, and still is, a
segment:offset architecture -- both in real and protected mode. Flat
mode is not a change to this architecture, it is simply a convention of
setting all of the segment registers to descriptors with a base address
of zero and a maximum limit.
:I now have a variant on my original
:question, assuming we now have a "flat" memory
:model, how are the interrupt vectors resolved?
From a hardware standpoint, it's the same as it has always been -- the
chip loads a segment:offset value from the Interrupt Descriptor Table
and transfers control. If you could look behind the protected mode
curtain, you would see the Great and Powerful OS manipulating the
controls.
:I've been reading that the interrupt vectors
:are in segment:offset notation, which would
:be meaningless if using absolute, 32-bit
:addressing schemes right?
If there were such a thing as an absolute 32-bit addressing mode
implemented in the chip, you would be correct. However, there is no such
thing. Flat mode is just a special way of using the segment registers so
that the user doesn't have to worry about them.
:I can really see why my basic 80x86
:assembly text states something to the effect
:that the protected mode instructions of the 80386
:and above processors are "beyond the scope of
:this book."
The protected mode instructions themselves are not all that complicated,
but they are definately beyond the scope of a basic assembly class,
because they were not intended to be used by application programmers.
Only those with in interest in writing (or understanding) operating
system components (including DOS extenders) need to learn protected mode
functions.
Best,
-- Chuck Crayne
寄件者：Olaf van der Spek (Spek@EuroNet.NL)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1998/01/14
>:If all addressing
>:in 32-bit OS's is 32-bit what use are the
>:various segment registers?
>None whatsoever! At least not at the user level. The innards of the OS
>are a different matter entirely.
Do all OS's use flat mode?
Otherwise the segment registers are of use for protection of data.
Mail to Spek@EuroNet.NL
Message 9 in thread
寄件者：ccrayne@pacific.net (ccrayne@pacific.net)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1998/01/14
In <69j7o8$dfq$2@winter.news.erols.com>, on 01/14/98
at 08:38 PM, Spek@EuroNet.NL (Olaf van der Spek) said:
:Do all OS's use flat mode?
:Otherwise the segment registers are of use for protection of data.
To the best of my knowledge, all of the protected mode operating systems
for the 80x86 hardware use the paging hardware for data protection.
Since page protection offers better security than segment protection,
there is no reason to use both methods. So they set the CS, DS, ES, and
SS registers to zero to simplify programming -- at least while
application programs are in control.
Best,
-- Chuck Crayne
-----------------------------------------------------------
ccrayne@pacific.net
-----------------------------------------------------------
comp.lang.asm.x86 moderation panel member
[This followup was posted to comp.lang.asm.x86 and a copy was sent to
the cited author.]
Message 10 in thread
寄件者：Jon Kirwan (jkirwan@reversit.moc.mocten.xi)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1998/01/15
On Wed, 14 Jan 98 14:12:15, ccrayne@pacific.net wrote:
>In <69j7o8$dfq$2@winter.news.erols.com>, on 01/14/98
> at 08:38 PM, Spek@EuroNet.NL (Olaf van der Spek) said:
>
>:Do all OS's use flat mode?
>:Otherwise the segment registers are of use for protection of data.
>
>To the best of my knowledge, all of the protected mode operating systems
>for the 80x86 hardware use the paging hardware for data protection.
>Since page protection offers better security than segment protection,
>there is no reason to use both methods. So they set the CS, DS, ES, and
>SS registers to zero to simplify programming -- at least while
>application programs are in control.
They don't set those registers to zero, for gosh's sake! That's the
NULL selector value. Bad news. Perhaps you meant that the base
address of the descriptor for the GDT/LDT entries pointed to by those
registers?
Btw, the term, flat, isn't very precise. I've heard it describe a
semantic where both the O/S and the applications all run at ring 0 and
share a common linear address space. It's safest to add a little
something when using the term to clarify it -- but it's even better to
avoid it, unless you are refering to a specific model taken in
conjunction with a particular O/S environment, like Win NT, for
example. One can always look up the meaning, then.
A flat application model usually means a situation where the CS
register has one selector, the DS, ES, SS, FS, and GS registers
another one. The CS must point to a code segment descriptor and the
others must point to a data segment descriptor. Both descriptors can
"map" the same linear address space, though.
Jon
Message 11 in thread
寄件者：ccrayne@pacific.net (ccrayne@pacific.net)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1998/01/15
In <69l64h$odg$3@winter.news.erols.com>, on 01/15/98
at 02:23 PM, "Jon Kirwan"<jkirwan@reversit.moc.mocten.xi> said:
:They don't set those registers to zero, for gosh's sake! That's the
:NULL selector value. Bad news. Perhaps you meant that the base
:address of the descriptor for the GDT/LDT entries pointed to by those
:registers?
Given the context of the original question, I had hoped that my
reference to setting segment registers to zero as an analogy to real
mode usage would be would be easier to understand by those who were not
familiar with protected mode internals, and forgiven by those who did.
However, since you misunderstood my meaning, I am sure that many others
also misunderstood. I should have compromised by saying "So they set the
CS, DS, ES, and SS registers to POINT TO zero to simplify programming --
at least while application programs are in control." Thank you for
bringing this to my attention.
:Btw, the term, flat, isn't very precise. I've heard it describe a
:semantic where both the O/S and the applications all run at ring 0 and
:share a common linear address space.
This semantic falls quite nicely within the generic model which I
described -- set the segment registers to point to zero and control
everything with the paging hardware.
:It's safest to add a little
:something when using the term to clarify it -- but it's even better to
:avoid it, unless you are refering to a specific model taken in
:conjunction with a particular O/S environment, like Win NT, for
:example. One can always look up the meaning, then.
Since I was attempting to avoid referring to a specific implementation,
I was using the term as defined in the Intel documentation [80386
Programmer's Reference Manual], from which I quote:
"In a 'flat' model of memory organization, the applications programmer
sees a single array of up to 2 [to the] 32 bytes (4 gigabytes). While
the physical memory can contain up to 4 gigabytes, it is usually much
smaller; the processor maps the 4 gigabytes flat space onto the physical
address space by the address translation mechanisms described in Chapter
5. Applications programmers do not need to know the details of the
mapping."
:A flat application model usually means a situation where the CS
:register has one selector, the DS, ES, SS, FS, and GS registers another
:one. The CS must point to a code segment descriptor and the others
:must point to a data segment descriptor. Both descriptors can "map"
:the same linear address space, though.
As you said, the term 'flat' is somewhat generic, but there is no need
to include the FS and GS registers in the flat model, and I do not
believe that this is usually done. In OS/2, to cite a specific example,
the FS register points to the Thread Information Block for the currently
executing thread, and the GS register points to an OS/2 internal control
block which is protected from user access.
Best,
-- Chuck Crayne
-----------------------------------------------------------
ccrayne@pacific.net
-----------------------------------------------------------
comp.lang.asm.x86 moderation panel member
Message 12 in thread
寄件者：Jon Kirwan (jkirwan@reversit.moc.mocten.xi)
主旨：Re: Flat memory models + BIOS addresses
新闻群组：comp.lang.asm.x86
View this article only
日期：1998/01/17
On Thu, 15 Jan 98 12:36:31, ccrayne@pacific.net wrote:
> Jon Kirwan said:
>:A flat application model usually means a situation where the CS
>:register has one selector, the DS, ES, SS, FS, and GS registers another
>:one. The CS must point to a code segment descriptor and the others
>:must point to a data segment descriptor. Both descriptors can "map"
>:the same linear address space, though.
>As you said, the term 'flat' is somewhat generic, but there is no need
>to include the FS and GS registers in the flat model, and I do not
>believe that this is usually done. In OS/2, to cite a specific example,
>the FS register points to the Thread Information Block for the currently
>executing thread, and the GS register points to an OS/2 internal control
>block which is protected from user access.
I described DS..GS register details and you quickly point out an O/S
where a clarification is important. Exactly my point!
We all have a tendency to not just simplify, but to over simplify; to
not just approximate, but to approximate to the point of distortion.
Some, without the background, will take it far too literally. Enough
of them will take a while to unwind the damage.
I guess my argument is this: My comment above approximates, but
doesn't do so to the point of distortion. It is liable to fu
--
※ 修改:·ysqcn 於 11月24日17:17:24 修改本文·[FROM: 211.69.197.81]
※ 来源:·UNIX编程 apue.dhs.org·[FROM: 211.69.197.81]
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